1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory allowing data stored therein to be erased in units of blocks.
2. Description of the Invention
The flash memory is one of those kinds of nonvolatile semiconductor memories which are capable of being electrically erasable. Flash memories are each erasable not in bytes but as a whole (all bits of the entire chip) or in units of blocks (a plurality of blocks constituting the chip). Because one memory transistor represents one bit in each flash memory, the flash memory may serve as an inexpensive nonvolatile memory.
The conventional flash memory outlined above will now be described with reference to some of the accompanying drawings. FIG. 17 is a schematic view showing a typical memory transistor structure of the conventional flash memory.
Referring to FIG. 17, the memory transistor comprises a P-type substrate 1, N+ diffused layers 2 and 3 each acting as a drain or a source, a control gate 4, a floating gate 5, and insulating films 6 and 7.
The N+ diffused layer 2 is used as the drain and the N+ diffused layer 3 as the source. In the memory cell array, the drain 2 is connected to a bit line, the source 3 to a source line, and the control gate 4 to a word line. At write time, the floating gate 5 captures electrons. When power is turned off, the floating gate 5 keeps intact the state it was in following the write operation. At erase time, the floating gate 5 releases the electrons it captured. The insulating film 6 is interposed between the floating gate and the substrate and is called a tunnel oxide film. The name of the film 6 is derived from the fact that at erase time, the electrons inside the floating gate 5 are released into the drain 2 or source 3 through tunneling. The insulating film 7 is interposed between the gate and the floating gate, and is usually formed with an oxide film about 200 A thick.
The relations between the gate voltage and the drain current in the memory transistor will now be discussed. As illustrated in FIG. 17, it is assumed that the drain 2, source 3 and control gate 4 are fed respectively with voltages VD, VS and VG, and that a current ID flows between the drain 3 and the source 3. FIG. 18 is a view showing the VG-ID characteristic of the memory transistor.
For a write operation on the memory transistor, a positive high voltage is given to the drain 2 and control gate 4, and a grounding potential is fed to the source 3. At this point, a channel is formed between the drain 2 and the source 3. While the channel allows a current to flow therethrough, hot electrons are generated in a depletion layer of the drain 2. An electrical field generated by the positive voltage fed to the control gate 4 causes the floating gate 5 to attract and capture the hot electrons. The electrons captured inside the floating gate 5 cause the threshold value Vth of the memory transistor to shift upward after the write operation, to become VthP shown in FIG. 18.
For an erase operation on the memory transistor, the source 3 is supplied with a positive high voltage. At this time, the control gate 4 is connected to the grounding potential and the drain 2 is allowed to float. This causes an electrical field between the source 3 and the floating gate 5 to develop tunneling, thereby, releasing the electrons captured by the floating gate 5 into the source 3. After the erase operation, the threshold value Vth of the memory transistor shifts downward, to become VthE in FIG. 18. In this manner, the flash memory allows data to be written thereto and erased therefrom in accordance with the status change of the threshold value Vth for the memory transistor.
The conventional flash memory having the above-described type of memory transistors will be described in more detail. FIG. 19 is a block diagram showing a typical structure of the conventional flash memory.
Referring to FIG. 19, the flash memory comprises a row address buffer RAB, a row decoder RD, a column address buffer CAB, a column decoder CD, memory address blocks MB0-MB7, erase circuits EE0a-EE7a, EE0b-EE7b, column gates CG0a-CG7a, CG0b-CG7b, sense amplifiers SA0a-SA7a, SA0b-SA7b, next-pulse control circuits NC0a-NC7a, NC0b-NC7b, output switching circuits OS0-OS7, and input/output buffers IOB0-IOB7.
The memory cell array blocks MB0-MB7 have 1K.times.1K (1K=1024) memory cells arranged into an array of 1M bits, comprising 1K word lines and 1K bit lines. The memory cell array blocks MB0-MB7 correspond respectively with input/output data D0-D7. Each of the memory cell array blocks MB0-MB7 is further divided into, say, two blocks. Illustratively, the memory cell array block MB0 is divided into blocks B0 and B0b. Corresponding respectively with the blocks B0a-B7a, B0b-B7b, there are provided the erase circuits EE0a-EE7a, EE0b-EE7b, the column gates CG0a-CG7a, CG0b-CG7b, the sense amplifiers SA0a-SA7a, SA0b-SA7b, and the next-pulse control circuits NC0a-NC7a, NC0b-NC7b. Furthermore, the input/output buffers IOB0-IOB7 and the output switching circuits OS0-OS7 are provided to correspond respectively with the input/output data D0-D7.
There exist 17 address signal lines. The address signals over the lines A0-A9 are input to the row decoder RD via the row address buffer RAB. The output of the row decoder RD causes one of a plurality of word lines WL to be selected. The remaining seven address signals A10-A16 are input to the column decoder CD via the column address buffer CAB. The output of the column decoder CD causes one of the multiple column gates CG0a-CG7a, CG0b-CG7b to conduct in accordance with the input/output data D0-D7. Then the bit line corresponding to the conducting column gate is selected.
For a write operation, the eight-bit input data D0-D7 is input to the sense amplifiers SA0a-SA7a, SA0b-SA7b via the input/output buffers IOB0-IOB7, the sense amplifiers acting as write circuits. The data is written to the memory cells selected as per the input data. That is, the desired data is written to the desired memory cells by applying a high voltage to the bit lines of the memory cells in question and by feeding the undesired memory cells with a low voltage such as the grounding potential. At this point, the selected word line is fed with the high voltage and the unselected word lines are connected to the grounding potential. As a result, data "1" is stored before the write operation (i.e., after erasure) and data "0" is stored after the write operation.
For a read operation, as in the case of the write operation, one word line is selected and so is one bit line with respect to each of the data D0-D7. The selected word line develops a read supply voltage VCC (usually 5 V), causing the corresponding one of the sense amplifiers SA0a-SA7a, SA0b-SA7b to operate. As discussed with reference to FIG. 18, when the word line has the voltage VCC (i.e., VG=VCC), the threshold value Vth of the memory cell in the erase state becomes lower than the supply voltage (i.e., VthE&lt;VCC), which allows the drain current ID to flow. The threshold value Vth of the memory cell in the write state becomes higher than the supply voltage (i.e., VthP&gt;VCC), which prevents the drain current ID from flowing. Thus the sense amplifiers SA0a-SA7a, SA0b-SA7b each check to see if the drain current ID flows. The result of the check is output via the output switching circuits OS0-OS7 to the input/output buffers IOB0-IOB7, whereby the output data D0-D7 is output.
For an erase operation, the source of each memory cell in question is fed with a high voltage via the erase circuits EE0a-EE7a, EE0b-EE7b. A plurality of (in this example, 2) erase circuits are furnished for each of the input/output data. The column gates and the sense amplifiers are also provided likewise. Each sense amplifier is connected to a next-pulse control circuit. Output signals N0a-N7a, N0b-N7b of the next-pulse control circuits are fed back to the corresponding erase circuits. Outputs S0a-S7a, S0b-S7b of the sense amplifiers are input to the corresponding output switching circuits. In turn, the outputs of the output switching circuits are input to the input/output buffers. When an erase instruction is executed, a first erase operation is carried out initially. The first erase operation is followed by the selection of an erase verify mode in which a check is made to see if the data in question is indeed erased. At this point, all sense amplifiers SAia, SAib (i=0-7) provided for the respective data are activated, and the column gates CGia, CGib are selected. This causes the data to be read from the applicable memory cells. That is, for each selected word line, the column gates corresponding to the erase circuits in question are selected. In this example, two column gates are selected for one selected word line. The data in the memory cells in question are read by means of the corresponding sense amplifiers and input to the corresponding next-pulse control circuits.
The next-pulse control circuits will now be described in more detail. FIG. 20 is a circuit diagram showing a typical structure of the next-pulse control circuits in FIG. 19. Referring to FIG. 20, each next-pulse control circuit includes NOR circuits G101 and G102.
The output terminal of the NOR circuit G101 is connected to one of two input terminals of the NOR circuit G102. The output terminal of the NOR circuit G102 is connected to one of two input terminals of the NOR circuit 101. The other input terminal of the NOR circuit 101 is supplied with a sense amplifier output signal Si. The other input terminal of the NOR circuit G102 is fed with an erase verify start signal EBSS. In this setup, the NOR circuits G101 and G102 constitute a flip-flop circuit. The erase verify start signal EBSS is a high-level one-shot pulse that is output at the start of an erase verify operation. The sense amplifier output signal Si is driven High when the data of the transistor making up the memory cell is "1," and brought Low when that data is "0."
When an erase verify operation is started, the erase verify start signal EBSS is input at the high level while the output Ni of the flip-flop circuit is fixed to the low level. In this state, the NOR circuit G101 receives the sense amplifier output signal Si that is output from the sense amplifiers in keeping with the memory cell data. For example, if the memory cell data is "0" (i.e., yet to be erased), the output Ni remains unchanged (i.e., an indication of the data not being erased). In this case, the erase circuit is activated in the next erase operation to erase the memory cell data. If the memory cell data is "1" (i.e., erasure judged complete), the output Ni is driven High. In this case, the erase circuit is inactivated in the next erase operation so as to suppress erasure. That is, the erase circuit is activated or inactivated depending on the output Ni of the next-pulse control circuit.
The output switching circuits will now be described in more detail. FIG. 21 is a circuit diagram showing a typical structure of the output switching circuits in FIG. 19. Referring to FIG. 21, each output switching circuit comprises a NAND circuit G103, an inverter G104, PMOS transistors Q101 and Q102, and NMOS transistors Q103 and Q104.
A transmission gate constituted by the transistors Q101 and Q103 receives a sense amplifier output signal Sib (e.g., output signal S0b of the sense amplifier SA0b) and a sense amplifier output signal Sia (e.g., output signal S0a of the sense amplifier SA0a). The gate of the transistor Q101 receives a control signal EV, and the gate of the transistor Q103 receives a control signal /EV. The control signal EV is driven High during an erase verify operation and brought Low otherwise; the control signal EV is the inverted signal of the control signal EV. (A slash "/" indicates an inverted signal hereinafter.) The sense amplifier output signals Sib and Sia are input to the NAND circuit G103. The NAND circuit G103 is connected to the inverter G104. In turn, the inverter G104 is connected to a transmission gate made up of the transistors Q102 and Q104. The gate of the transistor Q102 receives the control signal /EV, and the gate of the transistor Q104 receives the control signal EV. An output signal Oi is output by the two transmission gates, one composed of the transistors Q101 and Q103, the other constituted by the transistors Q102 and Q104.
The output switching circuit of the above structure operates as follows: a plurality of (in this example, 2) sense amplifiers are provided for each of the input/output data D0-D7. The output signals of these sense amplifiers are input to the corresponding next-pulse control circuits as well as to the single applicable output switching circuit. During an erase verify operation, the control signal EV is driven High and the control signal /EV brought Low. This turns on the transmission gate made up of the transistors Q102 and Q104, thus allowing the signal from the NAND circuit G103 to reach the output buffer via the inverter G104. That is, only if the outputs of the multiple sense amplifiers are all High, is the output signal Oi also High indicating the completion of data erasure. If at least one sense amplifier has a low-level output (prompting an "unerased" judgment), then the output signal Oi is Low. In this case, the entire chip remains unerased and is to be erased the next time. In the next-pulse control circuits, the outputs of the sense amplifiers are judged individually. The erase circuit connected to each memory cell judged to be erased stays inactive, so that no superfluous erase operation is carried out.
The flash memory is erased by one of two methods: an externally controlled erasure method whereby the erasure procedures outlined above are performed under external control, and an auto chip erasure method whereby all erasure-related operations are controlled from inside the chip. Under the auto chip erasure method, the process of erasure followed by the verification thereof is carried out repeatedly within the chip, until all addresses have been verified as erased.
Constituted as described, the conventional flash memory has each of its erase circuits checked for erasure during an erase verify operation. Even a single erase circuit judged to be unerased causes the ongoing erase verify operation to be halted and an erase operation to be resumed. The addresses are erased and then verified as erased one by one. This means that even if a memory cell connected to another erase circuit has in fact yet to be erased when a given address is reached, that memory cell is judged to be erased and remains undetected at that point. Only when the applicable address is reached, is the memory cell in question judged to be unerased and given an erase pulse. Because unerased memory cells at different addresses are erased using only the applicable erase circuits, the total erase time tends to be prolonged.